;------------------------------------------
; HC908 Example #3
;------------------------------------------

;Filename: example3.asm

;HC908QT/QY Programmer
;written by Kenrick Chin
;Version 1.00
;2003 Nov 21 - First writing

;This example is used to test the operation
;of the assembler and download process.
;Assembled code is written to flash memory.

;The internal oscillator at 12.8MHz is assumed.
;The timer prescaler bits in the TIM Status and Control
;Register (TSC) are set to binary 110 to select divide by 64.
;The 16-bit timer modulo registers are set to 25000
;causing the timer overflow flag (TOF) to be set
;once every 500ms.

;The output pins will flash once every second.

;labels used in the boot code are preceded with a dot (.)
;to avoid conflict with user programs

;------------------------------------------
; MCU Hardware Definitions
;------------------------------------------

SRAM   EQU  $80
DATA   EQU  $94
FLASH  EQU  $EE00

WATCHDOG EQU $FFFF

PORTA  EQU  $00
PORTB  EQU  $01
DDRA   EQU  $04
DDRB   EQU  $05

INTSCR  EQU $1D
CONFIG2 EQU $1E
CONFIG1 EQU $1F
OSCTRIM EQU $38

TSC     EQU  $20
TCNTH   EQU  $21
TCNTL   EQU  $22
TMODH   EQU  $23
TMODL   EQU  $24
TOF     EQU  7

COPD    EQU  0
RSTEN   EQU  0

;------------------------------------------------
; ROM routines
;------------------------------------------------

;AUX ROM jump vectors
GETBYTE   EQU $2800
RDRVRNG   EQU $2803
ERARNGE   EQU $2806
PRGRNGE   EQU $2809
DELNUS    EQU $280C

;MONITOR ROM routines
GETPUT    EQU $FE8E
PUTBYTE   EQU $FEA1
ONEBIT    EQU $FEC5

;ROM variables
CTRLBYT   EQU $88
CPUSPD    EQU $89
LADDR     EQU $8A
LADDR.H   EQU $8A
LADDR.L   EQU $8B
THEDATA   EQU $8C
MASSBIT   EQU 6

;------------------------------------------------
;         Communications Protocal
;------------------------------------------------

STX      EQU $3A       ;':'
ERAS     EQU $55       ;'U'
PGERAS   EQU $AA       ;'*'
PGM      EQU $25       ;'%'
RUN      EQU $4A       ;'J'

ACK      EQU $41       ;'A'
NACK     EQU $4E       ;'N'
CHK      EQU $58       ;'X'

;------------------------------------------------
;    Start of SRAM space used by binary loader
;------------------------------------------------

       ORG  DATA

.addr.H  DS   1
.addr.L  DS   1
.nbytes  DS   1
.sum     DS   1

;------------------------------------------------
; Bootstrap Loader
;------------------------------------------------

.boot  BOOT

       RSP

;mass erase
       BSET MASSBIT CTRLBYT
       LDHX #FLASH
       JSR  ERARNGE

.main  BSR   .getc
       STA   .sum    ;first byte
       CMP   #STX
       BNE   .main
       BSR   .getc
       CBEQA #PGM    .program
       BRA   .main

.program
       BSR  .getaddr
       BSR  .getc
       STA  .nbytes     ;save number of bytes
;assume bytes fall on page boundaries
;so that LADDR.H does not change
       DECA
       ADD  LADDR.L
       STA  LADDR.L
       LDHX #THEDATA    ;set buffer address
.next1 BSR  .getc       ;get data bytes
       STA  ,X          ;store data into buffer
       INCX             ;point to next address
       DEC  .nbytes
       BNE  .next1
       BSR  .getc       ;get checksum
       BEQ  .pgm
       LDA  #CHK        ;checksum error
       BRA  .ack

;setup for programming
;nbytes in THEDATA array
;H-X is destination address
;LADDR(2) is last destination address
;Globals: CPUSPD, CTRLBYT, THEDATA, LADDR(2)
.pgm   LDHX .addr.H
       JSR  PRGRNGE     ;program flash
       LDA  #ACK
.ack   JSR  PUTBYTE
       BRA  .main

;get next 2 bytes into addr.H, addr.L
;also preset LADDR.H, LADDR.L
.getaddr
       BSR  .getc
       STA  .addr.H
       STA  LADDR.H
       BSR  .getc
       STA  .addr.L
       STA  LADDR.L
       RTS

;get one byte and accumulate sum
.getc  JSR  GETBYTE
       PSHA
       ADD  .sum
       STA  .sum
       PULA
       RTS

       ENDB .boot

;------------------------------------------------
;       Start of Application
;------------------------------------------------

OSCK     EQU   115            ;oscillator trim for 12.8MHz
TIMEK.L  EQU   65

;------------------------------------------------
;       DATA Segment
;------------------------------------------------

        ORG  SRAM

;------------------------------------------------
;       CODE Segment
;------------------------------------------------

        ORG  FLASH

start   RSP
        BSET  COPD CONFIG1    ;turn off watchdog
        MOV   #OSCK OSCTRIM
        
;initialize PORTA and PORTB as outputs
       LDA   #$FF
       STA   DDRA
       STA   DDRB
       
;initialize timer
;set for MOD 2500 = $61A8
       MOV   #$61 TMODH
       MOV   #$A8 TMODL
;start timer, divide by 64 clock
       MOV   #%00010110 TSC

;-------------------------------------
;  main program loop
;-------------------------------------

main1  BRCLR TOF TSC main1
       STA   PORTA
       STA   PORTB
main2  BRCLR TOF TSC main2
       CLR   PORTA
       CLR   PORTB
       BRA   main1

;------------------------------------------------
;       Interrupt Vectors
;------------------------------------------------

        ORG  $FFFE
        FDB  start

        END
        
;------------------------------------------------
;       End of Example #3
;------------------------------------------------