| Objectives: To introduce the fundamentals of time dependent logic functions. |
Topics covered:
Digital circuits can be categorized into combinational logic and sequential logic. Combinational logic refers to a circuit whose outcome is a function of the inputs and does not depend on previous states. Gates, encoders, decoders, multiplexers, demultiplexers, read only memories (ROM), programmable logic arrays (PLA) are all examples of combinational logic.
Sequential logic incorporates time as an input parameter. The outcome of sequential logic depends not only on the present inputs but also on the previous state of the output. Examples of sequential circuits are flip-flops, latches, counters, registers, time-state generators.
Flip-flops are digital circuits used for retaining binary information. They are the basis for memory devices, latches, registers and counters. Flip-flops may function in a number of ways and are thus classified accordingly as shown.
| R-S | Reset-Set flip-flop |
| D | Data or Delay flip-flop |
| T | Toggle flip-flop |
| J-K | J-K flip-flop |
In practice, a flip-flop may contain a
combination of the above functions. For example, it is common for a flip-flop to contain the SET/RESET feature
as with the 7474 D-Type and 7476 J-K flip-flops as shown. (Sometimes SET and RESET are labelled as PRESET and CLEAR).
Note the usage of the bar over the signal names, e.g. S. Even though this represents the negation of S, it should not be considered as such. The bar over the S should be treated as part of the signal name and the combined name S should be considered as one name. Sometimes this is written as S*, S' or S(L). This notation is used to indicate a signal that is active-LO.
Similarly, the negation symbol should not be
considered as an inverter. Its purpose is to indicate that the associated input or output is an active-LO signal.
The operation of a flip-flop is governed by
the characteristics of the clock input. The output of the flip-flop will change only on the transition of the clock.
Some flip-flops will change on the rising edge of the clock while others will change on the the falling edge.
Flip-flops are available as edge-triggered and master-slave flip-flops. It is important to note the
difference between these two varieties. Special attention must be given to the timing diagram and data sheets.
On the rising
edge of the clock of a 7474 D-type flip-flop, the D-input is captured and the output Q will eventually change to
reflect this latched data. As one might expect, there is an area of uncertainty during which time the D-input must
not be changing. The device manufacturer specifies minimum data setup (tsu) and data hold
(th) times that must be adhered to if one is to expect reliable operation. After the rising edge of
the clock, there will be a propagation delay before the output changes. Again, the manufacturer will quote a maximum
propagation delay for LO-toHI (tPLH) or HI-to-LO (tPHL) transitions. See 74LS74 Data Sheet.
In the master-slave
flip-flop such as the 7476 J-K flip-flop, the transfer of data from the inputs and the change of the output occur
at opposite clock transitions. In this particular case, data is transferred on the rising edge of the clock while
the output changes on the falling edge. See 74LS76 Data Sheet.
What are flip-flops useful for? Here are various things that flip-flops are used for.
There are two basic ways of changing a flip-flop's state:
These two modes of operation behave quite differently. In (a), the flip-flop's clock input is edge sensitive. That is, the flip-flop changes state on one of the transitions of the clock. In (b), the flip-flop's set and clear inputs are level sensitive. That is, the flip-flop remains in the set or cleared state as long as the set or clear input is active. When designing with flip-flops it is important to carefully choose the mode of operation. The proper choice will depend on the specific application. It is common for both modes to be used together in the design.
A flip-flop is commonly used as a flag or semaphore. This is a hardware indicator or reminder that a certain event has occured or that the circuit is in a given state, for example, enabled vs disabled. Sometimes more than one flip-flop are required in order to distinguish the different conditions or states of the circuit. In these circumstances it is useful to consider the flip-flops together as a single time-state machine. In other words, firstly identify all the possible states required by the circuit and then, by design, incorporate the flip-flops in a group to match these states.
The T-type or toggle flip-flop is the basis for all binary counters. A single T-type flip-flop is a 1-bit counter. Its output toggles or changes state on one of the edges of the input clock. In other words, it counts, in modulo-2, the number of clock pulses appearing at the input. If you compare the input clock signal with the output of the flip-flop, you will see why this is also a divide-by-2 circuit.
An M-bit counter
can be created by cascading M stages of T-type flip-flops. This creates a divide-by-N counter where N =
2M. Such a counter is called a ripple counter since there is a ripple or domino effect as one
flip-flop overflows into the next stage. The propagation delay between the input clock and when the last stage
settles is the accumulated delay of each stage. Thus, all stages do not change at the same time. For this reason
a ripple counter is called an asynchronous counter.
In contrast to asynchronous
counters, synchronous counters are designed such that the outputs of all stages change simultaneously. All
stages are clocked from the same source and therefore are synchronized with each other. Synchronous counters may
be designed using any style of flip-flop and may be made to sequence through its states in any order.
Digital counters are available in a variety of styles. Their characteristics, features, differences and modes of operation should be observed.