8. System Structure

8.1 Introduction

In this section the method by which the digital elements of combinational and sequential circuits are organized into a simple operating system is examined. While a specific system will be emphasized a generic system may be envisioned encompassing modifications and embellishments of both components and techniques.

The basic system to be investigated is one which is capable of performing a predetermined series of instructions repetitively and is thus suitable for controlling an industrial process, for example.

8.2 Timing

The basic machine cycle will consist of 6 phases designated j_i,i=1,6. The time state generator is driven by the complement of the master clock signal.

All clocked devices are positively edge-triggered. As can be seen from the diagram, with this arrangement the clock edge is centred in the phase time frame, allowing for maximum set-up and hold time, when the time state phase signals control the flip flops.

8.3 Register Transfers

The register from which data flows is referred to as the source register (S). The registers to which data flows are referred to as the destination registers. The diagram shows six registers connected to a common bus. At any time there may be only one source register. The register outputs are connected to the bus through tri-state drivers. The active control signals are E₁, L₂ and L₆. The signal E₁ enables the tri-states, connecting the output of register 1 (R₁) to the bus, so R₁ is the source. The signals L₂ and L₆ connect the data inputs of the two destination registers R₂ and R₆ to the bus. These registers are then forced into the same state as R₁ with the arrival of the next clock edge. Both the enable and load signals are generated by the time state generator so that these levels both precede and persist beyond the clock edge as discussed in section 1.

8.4 Read Only Memories

A simple 4 address ROM with 6-bit word length is shown in the figure. The two-bit address a₁a₂ is decoded into the 4 minterms which then point to registers R₀,R₁,R₂,and R₄. The six bit lines run perpendicular to the address lines. The bit function is the OR of all addresses for which it is one.

In the example shown the register contents are:

R₀ 100101

R₁ 001011

R₂ 111001

R₃ 000100

thus for example

The bit lines are connected through tri-state buffers so the output is disconnected unless enabled. The connection to the memory address register MAR is asynchronous. The MAR is itself synchronous and is loaded with a new address at the clock edge following an active load signal. Of course in the arrangement shown the complementary outputs can be inverted before connection to the bus. A simplified diagram of the arrangement is shown in the accompanying illustration.

Activation of the load signal inputs the address word from the bus at the following clock edge. Once the MAR is loaded the ROM address lines are activated and the contents of the location to which the MAR points are present at the inputs to the tri-state drivers. When the enable is activated these are sent to the bus.

The form of read only memory shown in this example would be hard-wired. Other types are erasable and programmable so that the contents can in fact be changed. However this is done in a separate procedure and during operation of the digital system in which it is installed the ROM contents are constants. Formally the ROM is a combinational general digital function generator in which the output word to the bus X(A) is a defined function of the word A coding for the address. The list of contents shown above is in fact a group of six truth tables of which Eqn (8.1) is an example. An important common usage of ROMs is as permanent repositories of small start up programs which are automatically executed when power is applied to a larger digital system.

8.5 Random Access Memories

Since the contents of these devices may be changed during operation it is necessary that provision be made for both read and write operations. Random access memories are usually volatile, with the memory contents being lost when power is turned off. Non-volatile "flash memories" also exist. The volatile memories are also categorized as static and dynamic. The former retain their contents, once written, as long as power is on. Dynamic memories, based upon charge storage require refreshing periodically to correct for charge leakage.

A possible static RAM arrangement is shown in the diagram. Addresses are loaded into the MAR synchronously from the bus, and data into the MDR in the same fashion. The arrangement shown is for a tri-state RAM. The RAM control signals are memory enable (ME) and write enable (WE). If ME is not active the output to the bus is disconnected just as for a tristate driver. With the memory enabled and write not enabled the output lines connect to the bus so the contents of the location addressed by the MAR are read on to the bus. With both ME and WE active, the output to the bus is again disconnected and the contents of the MDR are written into the location addressed by the MAR.

8.6 A ROM Computer

The arrangement shown above comprises a digital system capable of performing a series of pre-programmed instructions resident in a ROM with 16 addresses of 8-bit words. The 4-bit program counter, PC, 4-bit memory address register, MAR, instruction register, IR, accumulator, ACC, B and output O registers, each 8-bits, are all clocked and have one or more connections to the 8-bit bus. The control unit CON consists of the clock, the time state generator and combinational circuits required to form the 12-bit control word each bit of which has the following function:

C_p: Program counter control. When high the PC counts up at clock time.

E_p: PC enable. When high connects the PC contents to the bus.

L_m: MAR load. When high MAR is loaded with bus contents at clock time.

E_r: MAR enable. Transfers ROM contents at address in MAR to bus.

L_i: IR load. ; E_i: IR enable. Connects 4LSB to bus ; L_a: Load A register ; E_a: Enable A register ; S_u: Subtract-add twos complement of word in B.

E_u: Enable ALU putting algebraic sum on bus

L_b: Load B register ; L_o: Load output register

8.7 Fetch Cycle

The fetch cycle is invariant, ie it is always the same no matter what instruction is to be carried out. It occupies 3 phases.

At f₁with the PC enabled the 4-bit address contained in the PC is put on to the bus. At clock time this address is loaded into the MAR since its load signal is high. The MAR immediately activates the lines of the ROM corresponding to the 8-bit instruction code word contained at the address present in the MAR. At f₂ the enable signal E_r connects the ROM data lines containing the instruction to the bus and a load signal is applied to the IR, defining it to be a destination. At clock time the contents of the bus corresponding to the instruction are loaded into the IR. In the third phase the count control signal is applied to the PC. At clock time the PC counter advances by one pointing to the address of the next instruction to be performed.

8.8 Instructions

This simple device has a very limited set of 5 instructions.

The instruction word is 8-bits in length. The 4 MSB of the word define the opcode field. The code is defined in the table above. For the subset of memory reference instructions, load accumulator, add and subtract the 4 LSB define the address field. This field is not used for the remaining two instructions. The three control words issued in the three phases of the instruction cycle depend upon the instruction the nature of which is determined by decoding the contents of the IR. This is why there is a direct 4-bit connection between the IR and controller. This connection is immediate and does not need to be enabled. As soon as the instruction is loaded during the memory phase the 4 MSB of the instruction appear at the decoder contained in the CON. The decoder output then determines the control words to be issued in the three phases of the execution cycle.

Memory reference instructions correspond to operations on data stored in memory. This data is known as the operand. The first phase of the execution cycle, f₄, for all MRIs is common and corresponds to setting up the MAR to point at the operand. This is given in the table below.

The 4 LSB of the IR are connected to the bus when E_i=1. Since L_m=1 then at clock time the MAR is loaded with the operand address.

The subsequent phases depend upon the instruction and are tabulated accordingly.

At f₅ the ROM is enabled connecting the output corresponding to the data at the location addressed in the previous phase to the bus. Since the accumulator load signal is also high in this phase, the data on the bus is loaded at clock time. Thus the task of loading the accumulator with data at the address contained in the instruction is completed. For this instruction phase 6 is not necessary. With a 6 phase time state generator, as the saying goes we have time on our hands. The control word of zero weight is a do nothing operation used in such a situation.

The ADD instruction requires all 3 phases of the instruction cycle. In f₅ register B is loaded with the contents of the address contained in the ADD instruction. In f₆ The algebraic sum from the ALU output is transferred to the bus since E_u is high. At the next clock pulse the bus contents are captured by the accumulator so that the sum replaces the original contents.

The sole difference for subtraction is that the control signal S_u is high at f₅ so that the twos complement of the content of register B is now added to that of register A in the ALU.

The OUT instruction only really requires one phase in which a data transfer from the accumulator to the output buffer register is executed. The remaining two phases are do nothing control words, i.e. F.

The HLT instruction does not involve any control words. Upon decoding of this instruction the clock is disabled shutting down the system.

8.9 Control Word Generation

The bits of the control words issued are logical functions of the time state generator phase signals and the 4-bit word of the opcode field of the instruction. The decoding of this 4-bit word into the five minterms m₀=LDA, m₁=ADD, m₂=SUB, m₁₄=OUT and m₁₅=HLT is straightforward. The combinational logic necessary to generate a given bit of the control word is determined by those phases and instructions requiring the one state. For example the bits C_p and E_p are only required during the third and first phases of the fetch cycle, giving the simple relations C_p=f₃ and E_p=f₁. The load memory address register is required both in the address phase of the fetch cycle and the beginning phase of any MRI. Thus the equation for this bit is

Similarly the ROM output is enabled during the memory phase of the fetch cycle and the fifth phase for any MRI giving

As a final example consider the load accumulator control bit L_a. This bit is high at the fifth phase for and LDA instruction when data is transferred from memory. It is also high at the sixth phase of ADD or SUB instructions When the result from the ALU is transferred to the accumulator. Thus the circuit logic is defined by

Continuing in this manner it is possible to find the logic conditions for all 12 bits of the control word. The control word is then generated using a matrix of AND and OR gates with appropriate inputs chosen from the set of six phases and five instructions.

8.10 Bidirectional Bus

The arrangement shown to the right produces a bidirectional bus connection thereby reducing the amount of wiring nearly a factor of two. In essence the output and input lines of the register are actually shorted and common lines connected to the bus. The shorted connections are internal.

The combination of the load and enable control signals prevents any completion of the shorted connection since in use the register is never operated with both signals high. The existence of a bidirectional bus is indicated more briefly by a double headed arrow.

8.11 Multi-dimensional Addressing

Let Y_M and X_N-M. Then the word Z=YX is defined as the concatenation of X and Y ie,

The set of all Z then define _N=_MN-M. Conceptually then the contents of two registers can be combined to generate words of length equal to the sum of the lengths of the two registers. In this way long effective word lengths may be achieved without physically constructing long registers. This is particularly useful in memory addressing, since the amount of memory addressed is limited by the length of the address register.

The relation between integers coded in standard fashion is

As a simple example consider N=5, M=2 and Y=11, X=101 so that Z=11101. Then from Eqn(8.6) the integer for which Z codes is given by 3x8+5=29, which of course is consistent with a direct interpretation of Z. Consider now an analysis of the relationship between the minterms of ₅ and those of ₂ and ₃ when the former set is constructed as the product of the latter. For the current example

The result of Eqn(8.7) is employed in the arrangement shown. Both Eqn(8.6) and (8.7) are most easily interpreted by visualizing the memory to be arranged as a 2-dimensional array with 2^N-M=4 rows (or pages) and 2^M=8 columns. The content of each register is decoded separately. The decoder outputs are the min terms corresponding to the row and column of the memory element being addressed. In this example the memory addresses are arranged as:

Row First Last

0 0 7

1 8 15

2 16 23

3 24 31

Extension to 3 or more dimensions is straightforward.