6. Sequential Circuits

6.1 Introduction

The output of the combinational circuits just discussed is uniquely determined by the input. For sequential circuits however, the output is dependent not only upon the input but the state of the circuit at the time the input is applied. The circuit exists in a series of states through time as inputs are applied. It is important to distinguish between the initial state of the system that exists before the input of interest is applied and the final state ultimately assumed after the input is applied. The latter is not achieved instantaneously, and allowance must be made for the associated delay. The initial state is normally designated as state n, indicating a series of prior states and the final state is then number n+1. The fundamental circuit upon which sequential circuits are based is the binary element, formally a bistable multivibrator but usually referred to as a flip-flop. The multivibrator family to which the flip-flop belongs is important in other respects and merits detailed discussion.

6.2 Multivibrators

Multivibrators are classified into three types, bistable, monostable and a stable. Their behaviour is illustrated by the simple mechanical analogies in the figure. The bistable monovibrator or flip-flop is analogous to the see-saw or teeter-totter of the children's playground. If an input in the form of a sufficient downward force is applied to the "up" end then it will assume the down position and the other end will move into the up position and remain there after the input is removed. Notice that further inputs corresponding to downward forces on this end would have no effect. Also notice that the state of the system could be described by the position of either end, and if logical variables are introduced to designate these states that these variables are complementary. The system exhibits the property of memory in that it remains in the state into which it has been set even though no further stimulus is required. In order to elaborate on this point somewhat further, let the position of one end be described by logical variable x and assume that force is only applied to one end. Moreover let the force be either up or down with positive being up. Now assume no force and x=0, representing down at the end of interest. As the force increases beyond a critical value the end will suddenly swing up to the x = 1 state. A further increase will leave the system at x = 1. Removing the force altogether will also leave the system with x = 1. In fact it is necessary to apply a negative (downward) force with magnitude exceeding the critical value to induce a transition back to the 0 state. The response of the system is shown in the diagram and has the form of a hysteresis curve. Physical systems exhibiting hysteresis are characterized as having memory. For example a wire under tension exceeding the elastic limit becomes permanently elongated. The strain remains even after the stress is removed, so that the system "remembers" it has been stretched. A compressive (negative) stress is necessary to return the wire to its original length. Of course the most famous example is ferromagnetism and ferromagnetic devices were one of the first forms of binary elements.

The second type of multivibrator, the monostable multivibrator, functions in an analogous manner to the teeter-totter in which one end is attached to a strong spring so that that end is down in the resting state and x = 0. A downward force applied to the opposite end will force this system to x = 1, but when the force is removed the system will return to x = 0, the only stable state. Electronic arrangements are capable of remaining in the x = 1 state for a period independent of the input so the mechanical analogy is only a rough one. The astable multivibrator is represented by the teeter-totter with both ends attached to springs. In the limit of negligible friction this system will oscillate back and forth between the two states continuously following a sharp downward force without any further inputs. In the case of electronic circuits oscillation is initiated by connecting the device to the power source.

6.3 Flip-Flops

6.3.1 Basic RS Flip-Flop

The basic flip flop is shown in the illustration and consists of cross coupled gates. The input labelled s is referred to as the set input, while the input r is the reset. Consider the situation s = 1,r = 0. Recall that the only NAND input giving rise to a zero output is two ones. Then q = 1 results in a self-consistent stable state with two 0 inputs at the upper gate and two 1 inputs at the lower gate. From symmetry q = 0 results from s = 0,r = 1. thus application of either of these two combinations forces the flip flop into the corresponding set or reset state. With s = 0, r = 0 either state is a self-consistent stable state since both NAND gates have at least one input line high. Thus whatever the initial state of the system application of two lows captures that state.

6.3.2 Clocked RS Flip-Flop

The RS flip-flop undergoes a transition for appropriate inputs. In a complex digital system the levels are dynamic and it is important to define precisely the time at which transitions take place thereby defining the time at which the correct state is assumed. This is accomplished by issuing a clock pulse, generated by an astable multivibrator, to all flip-flops in the system.

The arrangement is indicated in the figure in which the basic flip-flop is represented by the box. The AND gates ensure that the set and reset logic levels are only applied at clock time. Here the AND gates play the role of clock controlled switches. In the absence of the clock the system is in the hold mode with s = r= 0.

The clock pulse may itself be of significant duration. The device will be sensitive to changes on the input lines during the period the clock pulse is present. For this reason the clock pulse is normally shortened to a narrow spike before being applied to the two steering gates. This can be accomplished by differentiating the clock pulse. The assembly of differentiator and clocked flip-flop constitutes an edge-triggered flip flop since transitions are restricted to a narrow time at the edge of the clock pulse.

As indicated in the figure a triangle represents an edge triggered clock input. There are two possible edge triggering modes, positive edge or negative edge triggering. The latter is obtained by inversion of the differentiated signal so that the spike generated by the 1 to 0 falling edge becomes positive. This is indicated by the bubble. The narrow spikes may also be generated by circuits similar to that discussed in section 5.5 on propagation delay.

The behaviour of the flip flop is analysed in terms of two time segments that before the triggering edge for which the state of the flip flop is q_n and after the edge at which time the flip flop is in the new state q_n+1. Analysis may be made formally equivalent to that used for combinational circuits by treating q_n as an input variable along with r and s. The need to incorporate this variable arises because of the presence of feedback introduced by the cross coupling. As discussed in the previous section the truth table takes the form shown below.

The table and behaviour may be summarized in modes as follows:

inert s = 0,r = 0 then q_n+1 = q_n

reset s = x,r = 1 then q_n+1 = 0

set s = 1,r = x then q_n+1 = 1

As mentioned previously the states s = 1,r = 1 result in an indeterminate output and hence must not be allowed to occur in any practical operation. The output is given by the logical expression

for the allowed inputs. It implies a 1 output for the indeterminate case which is not necessarily correct, but this situation is not allowed.

6.3.3 Data Flip Flop

The data or D type flip flop as its name suggests is designed to capture the value of a data bit. The logical variable d representing the data bit is connected directly to the s input while its complement is connected to the r input. From Eqn(6.1)

Thus regardless of the initial state condition the final state assumes the value of the data input. This value will be held until the next clock pulse at which time it may be updated. The influence of the clock exists for a finite albeit short time around the edge. For proper operation it is necessary that the logical level d be established for an appropriate time preceding the clock edge. This time is referred to as the set-up time. The level must also be maintained for a time following the edge. This is referred to as the hold time. Clearly the time interval between clock pulses, which controls the ultimate speed with which a digital system performs must always exceed the sum of the set-up and hold times.

6.3.4 Toggle Flip Flop

The toggle (T) type flip flop is used in counting applications. The s and r inputs are internally connected, r to q and s to its complement, so that the only external input is the clock. The behaviour follows from Eqn(1) according to

Thus the final state assumed following the clock edge is always the complement of the initial state. The device thus toggles back and forth. As in all devices the time at which the final state is established follows the clock edge by the propagation delay. Thus the speed of toggling is limited to periods greater than this delay.

6.3.5 J-K Flip Flop

A versatile arrangement known as a J-K flip flop is shown in the diagram. The behaviour of the circuit can be analysed on the basis of Eqn(6.1). From the connections shown

where de Morgan's theorem has been used to expand the form of the complement of r. Substituting in Eqn(6.1)

The action may be summarized as follows. For the combinations j=0,k=0 or j=1,k=0 or j=0,k=1 the behaviour is identical to the RS flip flop with j=s and k=r. For j=1,k=1 the device becomes a toggle flip flop. A convenient aspect of this arrangement is that the indeterminate state of the RS flip flop cannot occur and all 4 combinations of the external inputs are allowed.

The behaviour is also summarized in the following table.

6.4 Monostable Multivibrators

An example of a monostable circuit is shown in the accompanying diagram. In the steady state the variable x = 1. Since p is connected to ground through resistor R this point is low in the steady state and y = 1. Thus both sides of the capacitor C are low. When the input x goes low briefly, then the NAND gate output goes high inducing a transient current through resistor R and creating an exponentially decreasing voltage at p. The output at y goes to 0 and remains at this level until the voltage at p decreases to the upper limit of the low range. At the time this point is reached the output returns to high and the circuit resumes the steady state. Suppose the voltage at p can be written

and that the upper limit corresponding to a low is v₀. Then the time duration of the output t_d is found from the requirement v_p(t_d)=v₀ . From Eqn(6.5) this leads to

The monostable output width can thus be controlled by the time constant of the differentiator circuit coupling the NAND and NOT gates. The associated wave forms in the figure are drawn assuming a time scale for which propagation delay is negligible.

The above circuit is an example of a non-retriggerable monostable multivibrator. A second input occurring within the time t_d will produce no effect. In the case of a retriggerable type, the return to equilibrium occurs at time t_d after the second input. Hence the output width is the sum of the spacing between inputs and the single input duration.

6.5 Gate Delay Generator

A common application of a monstable multivibrator is to generate a delayed logic signal x_d a specified time following the original signal x. This task is accomplished with the arrangement shown in the adjacent figure. The logic signal x is assumed to be a narrow positive spike. When inverted and presented to a monostable of the type discussed in section 6.5 the output is a negative going pulse of duration t_d. Differentiation of this signal produces a negative spike at t = 0 and a positive spike at t = t_d. The positive spike produces a delayed logic signal x_d at the input of any non-inverting one-input gate. Here an OR gate with the unused input set at 0 is used. The negative spike is treated as a zero input and ideally produces no output. The delay can be made variable by using a variable width monostable.

6.6 Astable Multivibrator

An example of an astable multivibrator is given in the accompanying diagram. In this arrangement an external CLOCK ENABLE logic input cen is included. Since multivibrators are a form of oscillator an external input is not necessary. The basic operation is easily understood and consists of a circulation of a complementary condition through a delay T_d. In the arrangement illustrated, when cen is low x is held high and the system is stable. When cen goes high the AND gate output goes high forcing x to go low. After a time T_d the AND gate output will follow x and go low forcing x to go high and so on. Thus a square wave is produced consisting of alternate low and high periods each of duration T_d. The period of oscillation is 2T_d. In general the duration of a high segment and low segment may differ. The ratio of the duration of a high segment to the period is the duty cycle. For this case the duty cycle is 0.5.