A digital-to-analogue converter accepts
an N-bit word input, X and produces a signal output v(X). It consists of an array of N linear gates and a resistor
network.A digital-to-analogue converter accepts
an N-bit word input, X and produces a signal output v(X). It consists of an array of N linear gates and a resistor
network.
An example for N = 3 is shown. The linear gates, which are shunt type, are gated by the three logical variables comprising the bits of the word X. The gate inputs are connected to a common reference voltage. The output from the kth gate can be written xkvref. The resistance connected to this output can be written as 2k-1R.
Assume that the output is grounded so that v(X) = 0. The current contributed through this resistor is then
Treated as a Norton equivalent circuit the strength of the current source is then
The sum on the extreme right hand side of Eqn(2) is the decimal integer represented by X in the standard unsigned binary integer code. The second parameter in the equivalent circuit is the source resistance. This is determined as the resistance between the unloaded output terminals with the input shorted (vref grounded). Under this situation the connection point between each resistor and the linear gate corresponds to ground independent of the value of the gating bit, xk, k = 1,N. If the gate is open by a high logic level the connection is to ground since the reference voltage is shorted. A closed shunt type linear gate output is always grounded. Hence all resistors in the network are in parallel. This leads to the relation for the source resistance Rs,
The source resistance is thus R/2, half the value of the smallest resistance in the ladder network. The source voltage, ie the voltage output for an infinite load resistance is vs(X) = iR/2 or
where I10(X) is the decimal digit coded by X. The output is not continuous but increases in increments of v0 = 2-Nvref, and is said to be quantized. With the source parameters established the equivalent circuit models may be used to give the output voltage for a finite load as
where RL is the load resistance.
The reference voltage may be a fixed value internal to the device. In a multiplying DAC, it is applied externally as a second input. As can be seen by Eqn(10) the output can be viewed as the product of the reference voltage and a fraction determined by the N-bit digital input, X.
Extension to signed integers in the twos complement representation is made possible by combining an offset voltage with a transformation of the code. Let X = {xi, i = 1,N} and X' = {xi, i = 2,N}, so that X' is constructed from the N-1 least significant bits of X. Then if C10(X) is the signed integer coded by X in the twos complement representation and I10(X) is the unsigned integer coded by X' in the standard binary integer code
Let Y = {yi, i=1,N} be constructed from X by complementing the most significant bit so that
Consider the case x1 = 0, so that C10(X) is positive. Then replacing the most significant bit by 1 is equivalent to adding 2N-1. In the case when x1 = 1 then C10(X) is negative. From Eqn(6) it is seen that the procedure is also equivalent to adding 2N-1. Thus for the twos complement representation complementing the most significant bit is equivalent to adding 2N-1 in all cases and the resultant lies in the normal unsigned range from 0 to 2N-1. This can be summarized by
The word Y is now converted to an analogue voltage vs(Y) = v0I10(Y) using the gate array and resistance network previously described. The final output vs(X)is achieved by subtraction of one-half the reference voltage, giving
Since the quantization voltage v0=vref/2N, the larger N the smaller the minimum step size and the smoother will be the output variation. The fineness of the quantization is referred to as resolution and is dictated by the number of bits. Thus for a 10-bit DAC the minimum step size is vref/210 , or approximately 0.1% of full scale. The output of the DAC is a digitally controlled fraction of the reference voltage so the device plays the role of a digital potentiometer.
4.1 Applications
Consider the arrangement shown in the
figure in which a multiplying DAC is included in the feedback loop of an operational amplifier. Since the output
signal is coupled to the DAC reference voltage input, the potential at the DAC output is I10(X)vout/2N.
Since the potential at the op-amp input is zero the current through the feedback resistor is vin/Ri,
which flows through the feedback resistor so that the DAC output must be at a potential of -Rfvin/Ri.
Equating the two expressions for the DAC output potential leads to the final result for the amplifier output as
Thus the arrangement produces an amplifier with a digitally controlled gain. It should be noted that X must not have 0 weight in this application, since this results in no feedback and consistent with Eqn(10) a saturated output.
A second very important application is shown in the next diagram which illustrates a precision programmable wave form or function generator.
Values of an arbitrary function f(xk) at equally spaced intervals xk = kDt are stored in consecutive addresses in a programmable read-only memory. The clock drives the N-bit counter to cycle through its 2N states, each of which corresponds to a PROM memory location. This action causes the memory contents to be sequentially sent to the DAC, the output of which will then be proportional to the sequence of stored function values. The time scale, represented conceptually by Dt, is controlled by the clock frequency. The above arrangement is extremely powerful because it incorporates a digital element, the PROM-DAC combination which provides enormous flexibility in the function generation. Virtually any finite mathematical function can be generated. Of course the output is only quasi-continuous, being a series of steps at the values stored in the PROM. These are of course also limited in precision by the PROM word length. However, the use of high resolution DAC's ,say 16 bits provides very high precision indeed.