Digital systems are used in data acquisition, process control and computation. They consist of a collection of interconnected registers and combinational circuits. The states of the registers are isomorphic to words, and the latter are defined codes of information. It is important to realize that codes may be defined arbitrarily. Thus a computer word by itself can only be interpreted as a description of an associated register state. Only when a specific code is defined can it be interpreted as information. Information is transferred from one register to another in a read/write operation. The contents of the source register are read and written into the destination register. This process is one in which the destination register is forced into the same register state as the source register. Information is generally transferred internally along a common path referred to as a bus. The bus consists of a set of conducting paths so that a single bit corresponds to a current level along one of the conductors. The current flow from the binary element of the source register forces the corresponding binary element of the destination register into the same state as the source. It is extremely important to note that the bus is a shared information path. Hence steps must be taken to ensure that its use is reserved at a specific time interval for a single source register. There may be more than one destination register. However it is also important to isolate those registers sharing the bus not intended as destination registers during this time interval.
Information is transferred to the external environment through ports. These are characterized by connectors so that connections may be physically altered. Ports and the associated communication of information occur as two basic types, serial and parallel. The former is exemplified by telegraph communications. The information flows on a single conductor. A word is transmitted as a series of current impulses, corresponding to successive bits of the word, one after the other. In a sense the N-bit word is received at a single spatial point in N time points. The parallel arrangement is analogous to the bus, with N conductors required, one for each bit. In this case the word is received at N spatial points at a single time point.
The system is organized so that specific registers or groups of registers perform specialized functions. In the case of the most versatile digital system, the computer, the behaviour of the system is dictated by a series of words which may be altered, code as instructions directing specific actions, and comprise a program.
Fundamentally memory consists of a set of M registers of length N. A common unit of length is the byte, N=8. Similarly metric-like prefixes of kilo, corresponding to 210 and Mega corresponding to 220 are used in describing memory size. An individual register of the memory is identified by a number, referred to as an address. The function of the memory is of course the storage of information. There is a variety of both physical and functional memory types. Functionally, a major distinction is that between memory that contains information which cannot be altered during operation of the system, read-only memory (ROM) and that which can be altered, random access memory (RAM). The former is further subdivided into memory manufactured with fixed information content, ROM and memory the contents of which can be altered in a special process, programmable read-only memory (PROM).
Stored in memory are words representing two types of information. The first type is information to be processed referred to generically as data. The second type is information describing how the processing is to be performed referred to as instructions. The set of all instructions define steps in the process and comprise a program. This distinction between the types of information represented is not intrinsic to the memory content which is always simply an N-bit word. The distinction must be defined by careful allocation of a subset of memory registers defined to contain instructions. All others then contain data by default. Such a subset of registers is referred to as a region of memory.
Two registers intimately associated with the memory unit are the memory address register (MAR) and the memory data register (MDR). The function of these two registers is largely explained in the terminology. The contents of the memory address register correspond to a word coding for the number of the memory register being accessed. The minimum required length L of the MAR is determined by the number M of memory registers. The MAR register set must have at least M members to code for the addresses so the condition on the length is 2L>=M. The contents of the memory data register correspond to the word in the memory location at the address contained in the MAR. The length of the MDR matches that of the memory register, N.
The program counter (PC), also referred to as the instruction pointer (IP), is a register that directs the flow of the program. The content of the PC at any time is a word coding for the address of the next instruction to be performed ie it "points to" the next instruction. The overall function of the PC in a given circumstance is illustrated by a flow chart. The allowed states of the PC then define the region of memory (subset of memory registers) allocated as those containing instructions. The allowed states comprise a subset of the PC register set. In programmable systems the allocation is flexible and is made as part of the programming. The same is true of the subset of PC register states and it is vital that this subset be consistent with memory allocation. It is impossible for the system to respond properly to a word representing data and not a member of the instruction set. The length of the PC matches that of the MAR.
The instruction register (IR) contains the word coding for the instruction currently being executed. The length of the register must match the length reserved for instructions. In the simplest arrangement an instruction is composed of a single word contained in memory and the length of the IR matches that of the memory registers. It is possible however to have an IR with length equal to a multiple of the memory register length. For example if the memory register length is one byte, and the length of the IR is 2 bytes it is possible to form 16-bit code words for instructions by writing one memory word into the least significant (rightmost) eight bits of the IR and a second into the most significant (leftmost) eight bits.
In performing a procedure, the digital system processes a series of instructions forming a program. The instructions are normally stored in a contiguous region of memory. The processing of each instruction is organized in time into two major cycles which have sub-intervals or phases. The major cycles are the fetch cycle and the execution cycle. In the fetch cycle the instruction is copied from its memory location to the instruction register. While the fetch cycle is unique the execution cycle varies depending upon the nature of the instruction. The fetch cycle consists of three phases, the address phase, the memory phase and the increment phase. During the address phase the contents of the PC are transferred to the MAR so that the memory location coded by the contents of the PC is accessed, setting the MDR to the contents of the location. In the memory phase the contents of the MDR are transferred to the IR. Thus all those addresses coded by the PC are defined to be instructions. In the increment phase the contents of the PC are altered to the word coding for the address of the next instruction. For example, suppose a program is located in consecutive memory locations beginning at 400. Then upon start up the binary word coding for 400, the starting address, will be loaded into the PC. Upon completion of the fetch cycle the word contained in memory location 400, coding for the first instruction, will be copied into the IR and the contents of the PC will be a word coding for the address 401.
The details of the execution phase depend upon the nature of the instruction. Examples will be discussed at a more appropriate time. Note that the fetch cycle is designed to produce a simple sequential order of execution. If one were to visualize the process by associating the addresses contained in the PC with points in space, then the process could be described as a straight line flow from starting point to finish. Such an arrangement is not always desirable however. For example, it might be necessary to repeat a subset of instructions a predetermined number of times. In this case the point would return to the first address of the subset each cycle and hence perform a looping motion. Finally, it might be desirable for the process to perform one of several alternative sets of instructions, chosen on the basis of an a priori condition. In this case the motion can be looked upon as following one of several alternative paths, or branches. The looping procedure is usually referred to as a WHILE DO programming construct and the branching procedure is referred to as an IF THEN construct. In both cases it follows that the contents of the PC must be altered in a manner different from that of the normal fetch cycle. This is done in the execution phase for the special class of instructions referred to as jump instructions. Flow charts are important diagrams which exhibit the manner in which a program containing jump instructions proceeds.
The ALU consists of special purpose combinational circuits including an adder, which as its name implies can perform the algebraic sum of two numbers. Details will be discussed at a later time. Also included are one or more registers referred to as accumulators, in which the results of arithmetic and logic operations are stored. Accumulators play a central role in programming operations with primary data being taken to an accumulator using a load command, and processed data from an accumulator using a store command. Since these commands must include information regarding the address of the source of or destination for the data they are examples of a class of instructions designated memory reference instructions.
Fundamentally the only arithmetic operations which can be performed using basic logic and register performance in a machine cycle are algebraic addition and multiplication or division by a factor of two. In order to perform more general multiply and divide operations fundamentally using the basic digital system these must be carried out as a sequence of the above add and scale by two operations. Thus the multiplication and division of two arbitrary numbers requires a set of instructions to perform the operation. For a program in which such common operations would be used frequently, inserting sets of instruction each time the operation were to be performed would lead to a great deal of repetition and programs of unwieldy length. The latter is not just a consideration of convenience. The longer a program the more memory will be required to contain it since each instruction requires the allocation of a memory location. This problem is solved by creating a subroutine, a self contained program within a program used to perform frequent operations. The complete program is then decomposed into a main program and subroutines, which are said to be called by the main program. For example, if a multiplication subroutine called MULT is included in the program, the task of the main program would be to assemble the two numbers to be multiplied and call MULT in such a manner as to pass these two numbers to the subroutine. Upon completion of the set of steps required it would then be necessary to return the product to the main program. This illustrates two features of subroutine usage. Firstly the subroutine should be written so that the data upon which it operates may be varied. Secondly implementation of the subroutine requires proper passing of data to and from the main program. A third consideration is program flow. Clearly the set of instructions comprising the subroutine will reside in a fixed area of memory. When a subroutine is called in the main program the PC contents, the address of the next instruction, must be altered to contain the starting address of the subroutine. Upon completion of the operation by the subroutine, the flow must return to the next instruction of the main program so the contents of the PC must be saved before alteration and restored as the last step of the subroutine operation to ensure a proper return.
As indicated in the above section, multiplication and division generally requires many machine cycles when performed with a basic system. This then contributes greatly to computation time when a program involving these common operations is used. Co-processors are digital subsystems designed to perform common mathematical operations much more quickly. A simple example would be a multiplication table. A ROM is constructed such that a pair of words representing multiplicands also codes for the address containing the corresponding product. This arrangement would be referred to as a hardware multiplier.
A stack is a special group of registers forming a memory together with a register called the stack pointer(SP) which form a first-in last out buffer. The stack pointer, like the program counter, contains the address of, or points to one of the registers comprising the memory. The contents of the stack pointer are also altered by one after each operation. Initially no information has been transferred to or from the stack, which is said to be empty. The address in the SP is that of register R1. When a word is written on the stack, referred to as a push operation, it is loaded into R1 and the SP contents are incremented to point to R2. This process is repeated for each push operation. Thus, for example, after five consecutive push operations the SP points to R6. The procedure of extracting a word from a stack is referred to as a pop operation. In the case above, a pop operation causes the SP to decrement, thus pointing to R5, the contents of which are then read from the stack. Continued pop operations then produce the contents of the stack in the reverse order to that in which they were written to the stack. Thus the five words written to the stack in the above example are written to the registers in the order R1,R2,R3,R4,R5 and are extracted from the stack in the order R5,R4,R3,R2,R1. One example illustrating the efficacy of the stack structure is that of nested subroutine calls. Consider the situation of a main program calling a subroutine S1 when it reaches address A1. The subroutine then in turn calls another subroutine S2 when it reaches address A2. Return to the main program is then a two step process in the reverse order. Return from S2 to S1 requires a jump to address A2+1, the contents of the PC at the time S2 was called by S1. Return from S1 to the main program similarly requires a jump to address A1+1, the address to which the PC was pointing when S1 was called by the main program. Thus if at each call the contents of the PC were loaded onto a stack, they would be popped off in the required order. Obviously this could be extended to nests of higher order.